Материал: DS12887

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DS12887

Figure 4. OUTPUT LOAD

Figure 5. BUS TIMING FOR MOTOROLA INTERFACE

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DS12887

Figure 6. BUS TIMING FOR INTEL INTERFACE WRITE CYCLE

Figure 7. BUS TIMING FOR INTEL INTERFACE READ CYCLE

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DS12887

Figure 8. IRQ RELEASE DELAY TIMING

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DS12887

Figure 9. POWER-UP/DOWN TIMING

POWER-UP/DOWN TIMING

 

 

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

at VIH before Power-Down

tPD

0

 

 

s

 

CS

 

 

 

VCC Slew from 4.5V to 0V (

 

 

at VIH)

tF

300

 

 

s

 

CS

 

 

 

VCC Slew from 0V to 4.5V (

 

 

 

at VIH)

tR

100

 

 

s

 

CS

 

 

 

 

 

at VIH after Power-Up

tREC

20

 

200

ms

 

CS

 

 

 

 

 

 

 

 

 

 

 

 

 

(TA = +25°C)

 

 

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

 

 

 

 

 

 

 

Expected Data Retention

tDR

10

 

 

years

 

Note: The RTC keeps time to an accuracy of 1 minute per month during data retention time for the period of tDR.

Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.

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