Status of External Pins During Idle and Power Down
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Mode |
Program Memory |
ALE |
PSEN |
PORT0 |
PORT1 |
PORT2 |
PORT3 |
Idle |
Internal |
1 |
1 |
Data |
Data |
Data |
Data |
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Idle |
External |
1 |
1 |
Float |
Data |
Address |
Data |
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Power Down |
Internal |
0 |
0 |
Data |
Data |
Data |
Data |
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Power Down |
External |
0 |
0 |
Float |
Data |
Data |
Data |
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Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Lock Bit Protection Modes (1)
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Program Lock Bits |
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LB1 |
LB2 |
LB3 |
Protection Type |
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1 |
U |
U |
U |
No program lock features. |
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2 |
P |
U |
U |
MOVC instructions executed from external program memory are disabled from fetching code bytes from internal |
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memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. |
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3 |
P |
P |
U |
Same as mode 2, also verify is disabled. |
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4 |
P |
P |
P |
Same as mode 3, also external execution is disabled. |
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Note: |
1. |
The lock bits can only be erased with the Chip Erase operation. |
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Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash
The AT89LV51 is normally shipped with the on-chip Flash memory array in the erased state (i.e. contents=FFH) and ready to be programmed.
The respective top-side marking and device signature codes are listed below:
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VPP = 12V |
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AT89LV51 |
Top-Side Mark |
xxxx |
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yyww |
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(030H)=1EH |
Signature |
(031H)=61H |
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(032H)=FFH |
The AT89LV51 code memory array is programmed byte- by-byte. To program any non-blank byte in the on-chip Flash Code Memory, the entire memory must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the AT89LV51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 2 and Figure 3. To program the AT89LV51, the following sequence should be followed:
1.Input the desired memory location on the address lines.
2.Input the appropriate data byte on the data lines.
3.Activate the correct combination of control signals.
6 |
AT89LV51 |
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AT89LV51
4.Raise EA/VPP to 12V if in the high-voltage programming mode.
5.Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5 changing the address and data for the entire array or until the end of the object file is reached.
Data Polling: The AT89LV51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash array and the lock bits are erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-pro- grammed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are:
(030H) = 1EH indicates manufactured by Atmel
(031H) = 61H indicates 89LV51
(032H) = FFH (High-Voltage)
Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.
Flash Programming Modes
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ALE/ |
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Mode |
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RST |
PSEN |
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EA/VPP |
P2.6 |
P2.7 |
P3.6 |
P3.7 |
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PROG |
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Write Code Data |
H |
L |
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H/12V |
L |
H |
H |
H |
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Read Code Data |
H |
L |
H |
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H |
L |
L |
H |
H |
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Write Lock |
Bit - 1 |
H |
L |
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H/12V |
H |
H |
H |
H |
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Bit - 2 |
H |
L |
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H/12V |
H |
H |
L |
L |
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Bit - 3 |
H |
L |
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H/12V |
H |
L |
H |
L |
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(1) |
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Chip Erase |
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H |
L |
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H/12V |
H |
L |
L |
L |
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Read Signature Byte |
H |
L |
H |
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H |
L |
L |
L |
L |
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Note: 1. |
Chip Erase requires a 10 ms |
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pulse. |
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PROG |
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Figure 2. Programming the Flash |
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Figure 3. Verifying the Flash |
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Flash Programming and Verification Characteristics
TA = 0°C to 70°C, V CC = 5.0V ± 10%
Symbol |
Parameter |
Min |
Max |
Units |
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(1) |
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Programming Enable Voltage |
11.5 |
12.5 |
V |
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VPP |
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(1) |
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Programming Enable Current |
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25 |
μA |
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IPP |
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1/tCLCL |
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Oscillator Frequency |
4 |
12 |
MHz |
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tAVGL |
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Address Setup to |
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Low |
48tCLCL |
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PROG |
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tGHAX |
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Address Hold After |
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48tCLCL |
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PROG |
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tDVGL |
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Data Setup to |
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Low |
48tCLCL |
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PROG |
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tGHDX |
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Data Hold After |
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48tCLCL |
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PROG |
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tEHSH |
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P2.7 |
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High to VPP |
48t CLCL |
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(ENABLE) |
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tSHGL |
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VPP Setup to |
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Low |
10 |
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PROG |
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(1) |
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μs |
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VPP Hold After PROG |
10 |
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tGHSL |
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tGLGH |
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Width |
1 |
110 |
μs |
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PROG |
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tAVQV |
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Address to Data Valid |
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48t CLCL |
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tELQV |
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Low to Data Valid |
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48tCLCL |
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ENABLE |
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tEHQZ |
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Data Float After |
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0 |
48tCLCL |
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ENABLE |
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tGHBL |
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High to |
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Low |
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1.0 |
μs |
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PROG |
BUSY |
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tWC |
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Byte Write Cycle Time |
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2.0 |
ms |
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Note: 1. Only used in 12-volt programming mode.
8 |
AT89LV51 |
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AT89LV51
Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)
P1.0 |
- |
P1.7 |
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PROGRAMMING |
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VERIFICATION |
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ADDRESS |
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ADDRESS |
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P2.0 |
- |
P2.3 |
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tAVQV |
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PORT 0 |
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DATA IN |
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DATA OUT |
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tAVGL |
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tDVGL tGHDX |
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tGHAX |
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ALE/PROG |
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tSHGL |
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tGLGH |
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tGHSL |
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VPP |
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LOGIC 1 |
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EA/VPP |
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tEHSH |
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LOGIC 0 |
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tEHQZ |
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tELQV |
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P2.7 |
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(ENABLE) |
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tGHBL |
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P3.4 |
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BUSY |
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(RDY/BSY) |
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READY |
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tWC |
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||||
Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)
P1.0 |
- |
P1.7 |
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PROGRAMMING |
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VERIFICATION |
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ADDRESS |
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ADDRESS |
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P2.0 |
- |
P2.3 |
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tAVQV |
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PORT 0 |
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DATA IN |
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DATA OUT |
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tAVGL |
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tDVGL tGHDX |
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tGHAX |
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tSHGL |
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tGLGH |
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LOGIC 1 |
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LOGIC 0 |
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tEHSH |
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tELQV |
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tEHQZ |
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P2.7 |
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(ENABLE) |
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tGHBL |
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P3.4 |
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BUSY |
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(RDY/BSY) |
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READY |
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tWC |
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9
Absolute Maximum Ratings*
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*NOTICE: |
Stresses beyond those listed under “Absolute Maxi- |
Operating Temperature ........................ |
-55°C to +125°C |
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mum Ratings” may cause permanent damage to the |
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device. This is a stress rating only and functional |
Storage Temperature............................ |
-65°C to +150°C |
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operation of the device at these or any other condi- |
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tions beyond those indicated in the operational sec- |
Voltage on Any Pin |
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tions of this specification is not implied. Exposure to |
with Respect to Ground........................... |
-1.0V to +7.0V |
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absolute maximum rating conditions for extended |
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periods may affect device reliability. |
Maximum Operating Voltage ................................... |
6.6V |
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DC Output Current ............................................ |
15.0 mA |
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DC Characteristics
TA = -40°C to 85°C, V CC = 2.7V to 6.0V (unless otherwise noted)
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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VIL |
Input Low Voltage |
(Except |
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-0.5 |
0.2 VCC - 0.1 |
V |
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EA) |
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VIL1 |
Input Low Voltage |
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-0.5 |
0.2 VCC - 0.3 |
V |
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(EA) |
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VIH |
Input High Voltage |
(Except XTAL1, RST) |
0.2 VCC + 0.9 |
VCC + 0.5 |
V |
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VIH1 |
Input High Voltage |
(XTAL1, RST) |
0.7 VCC |
VCC + 0.5 |
V |
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VOL |
Output Low Voltage (1) |
IOL = 1.6 mA |
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0.45 |
V |
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(Ports 1,2,3) |
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VOL1 |
Output Low Voltage (1) |
IOL = 3.2 mA |
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0.45 |
V |
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(Port 0, ALE, PSEN) |
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IOH = -60 μA, VCC = 5V ± 10% |
2.4 |
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V |
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VOH |
Output High Voltage |
IOH = -20 μA |
0.75 VCC |
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V |
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(Ports 1,2,3, ALE, |
PSEN) |
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IOH = -10 μA |
0.9 VCC |
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V |
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IOH = -800 μA, VCC = 5V ± 10% |
2.4 |
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V |
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VOH1 |
Output High Voltage |
IOH = -300 μA |
0.75 VCC |
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V |
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(Port 0 in External Bus Mode) |
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IOH = -80 μA |
0.9 VCC |
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IIL |
Logical 0 Input Current |
VIN = 0.45V |
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-50 |
μA |
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(Ports 1,2,3) |
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ITL |
Logical 1 to 0 Transition Current |
VIN = 2V, VCC = 5V ± 10% |
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-650 |
μA |
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(Ports 1,2,3) |
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ILI |
Input Leakage Current |
0.45 < VIN < VCC |
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±10 |
μA |
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(Port 0, EA) |
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RRST |
Reset Pulldown Resistor |
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50 |
300 |
KΩ |
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CIO |
Pin Capacitance |
Test Freq. = 1 MHz, TA = 25°C |
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10 |
pF |
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Power Supply Current |
Active Mode, 12 MHz, VCC = 6V/3V |
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20/5.5 |
mA |
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ICC |
Idle Mode, 12 MHz, VCC = 6V/3V |
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5/1 |
mA |
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Power Down Mode (2) |
VCC = 6V |
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100 |
μA |
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VCC = 3V |
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20 |
μA |
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10 |
AT89LV51 |
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