Материал: Ускоренный курс английского языка для проектировщиков сверхбольших интегральных схем. Каширский С.Н., Балашов Ю.С

Task 10. Skim the following text and try to understand the subject-matter

of the text.

TEXT 1C:

A MULTILEVEL, HOLISTIC VIEW OF DESIGN FOR LOWER POWER CONSUMPTION

Designers are looking to different sources for reduction of power consumption, and will ultimately see that the solutions are required in all stages of the design. An effective power management flow would need to attack the issues in a top-down fashion, from the highest opportunity – which is in the RTL synthesis and gate optimization – to the implementation phase, and finally the validation of design integrity. The seemingly complex solutions, however, need to be cohesively thought out, so that the best QoS can be achieved and be easily applicable to reduce barriers to efficient design.

The Encounter platform’s low-power design flow addresses the power management issue with multilevel solutions throughout the design flow. A summary of the flow is shown in Figure 2.

Figure 2: Power management and the design flow

Task 11. Find sentences with the following words.

1. Power consumption – потребление мощности.

2. Power management – управление мощностью.

3. Routing – трассировка.

4. Electrical verification – электрическая проверка.

Task 12. Comprehension check:

1. What are designers looking to?

2. What can you tell us about effective power management?

3. Look at fig.2 and sum up the power management and the design flow.

Task 13. Match up the words with the definition.

ACTIVITY 2

Task 14. Skim the following passage and try to understand the subject-matter of it.

TEXT 2A:

DYNAMIC POWER MANAGEMENT

Dynamic power dissipation occurs when a circuit is operating. As shown in the equation (see Appendix), this switching power can be controlled by limiting the amount of capacitance switching or limiting the frequency of operation. But maximum power savings are achieved by reducing the voltage, as this term has a quadratic effect on power. Technology scaling offers maximum benefit in this area until process technologies reach 130 nm, where the operating voltages are close to the threshold voltage of the transistor. For technologies below 130 nm, designers are looking at other ways of controlling voltage. Designing with multiple supply voltages (voltage “islands”) is becoming essential for many applications, and new tools to facilitate this process are being developed.

Task 15. Comprehension check:

1. What is dynamic power?

2. How are maximum power savings achieved?

3. Which way of controlling voltage are designers looking at?

4. What is becoming essential for many applications?

Task 16. Fill in the gaps with the correct variant.

1. Dynamic power ….. occurs when a circuit is operating.

a) result b) dissipation c) event

2. This switching power can be ….. by limiting the amount of capacitance switching or limiting the frequency of operation.

a) achieved b) produced c) controlled

3. Maximum power ….. are achieved by reducing the voltage, as this term has a quadratic effect on power.

a) changes b) savings c) economies

4. Designers are looking at other ….. of controlling voltage.

a) problem b) challenge c) way

Task 17. Sum up the text using the following plan.

1. Dynamic power.

2. Maximum power.

3. Voltage “islands”.

Task 18. Skim the following passage trying to understand it and give a title to it.

TEXT 2B:

As CMOS process density has increased, leakage power dissipation has become a major issue, because it occurs even when a circuit is in idle mode. Leakage power dissipation can account for more than 50% of total power dissipation in 65-nm ICs. Effective strategies for addressing leakage power dissipation are just beginning to emerge. One is the design methodology of multiple voltage thresholds (Vt), which entails placing low-Vt cells on the critical paths and high-Vt cells on noncritical paths during both the logic and physical synthesis stages. Other techniques that control leakage power involve significant changes in design methodology. Many designers are considering techniques such as reverse biasing the substrate or just lowering substrate voltage.

Task 19. Comprehension check.

1. Where does leakage power dissipation take place?

2. What is the design methodology of multiple voltage thresholds?

3. Which techniques are used by designers to low substrate voltage?

Task 20. Skim the following passage try to understand the subject-matter of it.

TEXT 2C:

DYNAMIC POWER OPTIMIZATION

There are two excellent sources for reduction of dynamic power dissipation: reducing the switching activity (f) and reducing the effective capacitance (C). Register transfer level (RTL) and micro-architecture offer a great opportunity to influence dynamic power. Encounter RTL Compiler does a concurrent optimization of timing, area, and power during RTL elaboration, global structural optimization, direct target-guided optimization, and global technology mapping, which form the basis for synthesis. The global-focused approach results in better optimization across all these metrics. These optimizations target reducing the overall capacitance. The result is that the design has a higher QoS. Apart from the power aware capacitance optimization, specific power optimization features that can optimize the switching of the clock network are also effective techniques.

Task 21. Comprehension check:

1. How many sources for reduction dynamic power dissipation do you know?

2. What does Encounter RTL Compiler do?

3. What is the result of dynamic power dissipation?

Task 22. Skim the passage and find out the example of RTK clock gating.

TEXT 2D:

RTL CLOCK GATING

In many instances, data is loaded into registers infrequently, but the clock signal continues to switch at every clock cycle, which drives a large capacitive load. Registers are assigned the same value for every clock cycle. To prevent the clock from triggering the registers, a gating circuit can be used to shut off the clock from these registers. Clock gating alone can result in a 30% to 60% power savings. Figure 3 shows a typical clock-gating circuit.

Figure 3: Example of clock gating, in both logic and implementation

Traditionally, the clock gating would be part of the design process, which could require additional and complicated design effort. The newest version of Encounter RTL Compiler can perform an automated clock-gating function, using integrated clock-gating cells from a library as well as user-defined logic. This feature is possible because Encounter RTL Compiler recognizes opportunities in the logic design, and inserts clock gating from the RTL or from a gate-level netlist with a simplified process.

To enable design integrity verification, Encounter RTL Compiler also ensures that the clock signal can be observed and controlled for DFT purposes, through added test observability and controllability logic in the gating cells, and integrated capabilities for interfacing with Encounter Test within the Encounter Platform.

Task 23. Find out the sentences with the following words:

RTL – resistor-transistor logic – резисторно-транзисторные логические схемы (логика)

Encounter RTL Compiler – компилятор

Clock cycle – тактовый цикл

Gating circuit – вентильная схема

DFT – discrete Fourier transform – дискретное преобразование Фурье, ДПФ

Task 24. Which of the following do you think are true or false?

1. Clock gating requires design completed effect.

2. Figure 3 shows a typical integrated circuit

3. Encounter RTL Compiler ensures that clock signal can be absorbed and controlled for DFT purposes.

Task 25. Study the following words and word combinations in the following sentences:

Decloning and cloning – разделение и объединение логических вентилей

Clock tree – («клоковое дерево») цепь тактового сигнала

Layout view – топологическая схема

Task 26. Skim the text and try to get its main idea.

TEXT 2 E:

GATING LOGIC DECLONING AND CLONING

A method of minimizing the overall capacitance on the clock tree involves manipulating the gating logic. In the logic view, after insertion or recognition of clock gating, the clock-gating element can be combined and moved upstream in the hierarchical tree to reduce the amount of gating cells (decloning) and switch off the larger branch of logic. At the same time, this simplifies the clock network structure for physical design. Encounter RTL Compiler has the pruning capability as a post-synthesis technique.

Figure 4: Decloning and cloning of the clock-gating logic

In the layout view, the register partitions created by the clock-gating logic may not be localized. The gating logic might not be placed close to the register that it controls, but might be closer to other registers controlled by different gating logic. Using the Encounter platform, designers can analyze the placement of all the registers and merge clock-gating instances with the same control signals. This reduces the fragmentation of gating logic. Then, they can clone the gating logic to newly grouped registers to reduce the overall capacitance. Figure 4 illustrates decloning and cloning of clock-gating logic.

Task 27. Look at the fig.4 and discuss the problem of cloning / decloning:

Task 28. Read the following text and try to understand the subject-matter of it.

TEXT 2F:

LOW-POWER CLOCK TREE SYNTHESIS AND ROOT GATING

The clock network is usually the largest network in a chip and is a major variable in dynamic power consumption. This network connects all the registers and contributes a huge capacitance. The clock network also has the highest switching probability (p = 1), because it switches twice in every cycle. The switching power dissipation due to the clock signal is enormous and can account for 30% to 50% of the overall power dissipation. Therefore, power must be considered when the clock network is constructed. Encounter clock tree synthesis can build clock trees while minimizing overall insertion delay by decreasing the number of levels, minimizing skews by balancing the tree, and reducing overall capacitance by selecting appropriate clock buffers. The patented smart clustering algorithm clusters the clock targets first, before building a top-down tree. Further, to save switching power while balancing skews, the algorithm can insert buffers past the gating elements so buffers are active only during the real operation.

Figure 5: Root gating

Another technique for saving power is to shut down the clock branches by identifying sets of clock-gating instances driven by the same clock, based on physical proximity. Designers can use a command in the tool to insert gating logic at the root of the clock to save the power consumed by the clock tree network feeding those instances (see Figure 5). The gating signal for the new root-gating logic is a Boolean OR of the gating signals of the clock-gating instances.

Vocabulary work and situations.

Task 30. Guess the meanings of the following word and word combination.

RTL-to-GDS flow

Leakage power

Encounter RTL Compiler

Power management

Routing

Electrical verification

Task 31. Try to recognize the word in the following sentences and translate them into Russian.

1. A balanced approach is warranted when it comes to power optimization that spends across the entire RTL-to GDS flow.

2. Dynamic power dissipation occurs when a circuit is operating.

3. Register Transfer Level (RTL) and micro-architecture offer a great opportunity to influence dynamic power.

4. Encounter RTL Compiler does a concurrent optimization of timing, area, and power during RTL elaboration.

Task 32. Define the meaning of such word using the English-English dictionary. The first example in given to you.

Consumption – an act of consuming and using.

Solution

Flow

Power

Task 33. Match up the words with the definition.

SITUATIONS:

1. Use Fig.2 and give explanation about power management.

2. Discuss the aspects of power awareness.

3. Comment upon new systems and architecture design.

4. Share your opinion of the power management of design flow.

OUTCLASS ACTIVITY

Task 34. Read the text and pay attention to the multiple “voltage islands”.

DESIGN WITH MULTIPLE VOLTAGE ISLANDS

Voltage scaling is an obvious technique to gain significant power saving for any low-power design. In an example of reducing the voltage from 1.0V to 0.8V (20% reduction), while assuming both the capacitance (C) and the switching frequency (f) remain the same, one would gain up to 36% dynamic power reduction. This emerging design approach can have a major impact on optimizing power consumption, and promises to become an effective strategy. The technique is based on “islands” of cells, each with different supply voltages (Vdd). The less timing-critical logic can have a scaled-down voltage supply, at a cost of slower timing performance. These voltage islands can even be turned off completely when not in use. When a signal goes through these islands, it needs to pass through level shifters to keep it at appropriate voltages and also clamp cells, in case islands are turned off.