Материал: mmdf4c03hdrev1

t, TIME (ns)

td(on)

1.0

1.0 10

RG, GATE RESISTANCE (OHMS)

RG, GATE RESISTANCE (OHMS)

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses.

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high

N±Channel

5.0

4.5VGS = 0 V

TJ = 25°C

VSD, SOURCE±TO±DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy.

Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

Figure 10. Diode Forward Voltage versus Current

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain±to±source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, ªTransient Thermal Resistance ± General Data and Its Use.º

Switching between the off±state and the on±state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed

(TJ(MAX) ± TC)/(RθJC).

A power MOSFET designated E±FET can be safely used in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non±linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E±FETs can withstand the stress of drain± to±source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

VDS, DRAIN±TO±SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN±TO±SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad geometry, the packages will self±align when subjected to a solder reflow process.

The power dissipation of the SO±8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is

determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the

device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO±8 package, PD can be calculated as follows:

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into

the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.

The 62.5°C/W for the SO±8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad . Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

•Always preheat the device.

•The delta temperature between the preheat and soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed 260°C for more than 10 seconds.

•When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied during cooling.

* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.