Материал: FSDM311_FAIR
www.fairchildsemi.com
FSDM311
Green Mode Fairchild Power Switch (FPSTM)
Features
•Internal Avalanche Rugged Sense FET
•Precision Fixed Operating Frequency (67kHz)
•Advanced Burst-Mode operation Consumes under 0.2W at 265Vac and no load
•Internal Start-up Switch and Soft Start
•Under Voltage Lock Out (UVLO) with Hysteresis
•Pulse by Pulse Current Limit
•Over Load Protection (OLP)
•Over Voltage Protection (OVP)
•Internal Thermal Shutdown Function (TSD)
•Secondary Side Regulation
•Auto-Restart Mode
TYPICAL POWER CAPABILITY
PRODUCT |
Open Frame |
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230VAC ± 15%(1) |
85-265VAC |
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FSDM311 |
20W |
12W |
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FSDM311L |
20W |
12W |
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Table 1. Notes: 1. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
Applications
•Charger & Adaptor for Mobile Phone, PDA & MP3
•Auxiliary Power for White Goods, PC, C-TV & Monitor
Description
The FSDM311 is an integrated Pulse Width Modulator (PWM) and Sense FET specially designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. This device is a monolithic high voltage power switching regulator which combines an VDMOS Sense FET with a voltage mode PWM control block. The integrated PWM controller features include: a fixed oscillator, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/ turn-off driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDM311 reduces total component count, design size, weight and at the same time increases efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters.
AC
IN 
DC OUT
Vstr |
Drain |
PWM |
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Vfb Vcc Source
Figure 1. Typical Flyback Application using FSDM311
Rev.1.0.4
©2004 Fairchild Semiconductor Corporation
FSDM311
Internal Block Diagram
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Vstr |
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5 |
6,7,8 |
Drain |
Vcc |
2 |
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L |
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UVLO |
Voltage |
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Internal |
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H |
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Ref |
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Bias |
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8.7/6.7V |
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OSC |
Vck |
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5uA |
400uA |
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DRIVER |
SFET |
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PWM |
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S |
Q |
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Vfb |
3 |
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R |
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S/S |
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15mS |
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BURST |
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VBURST |
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LEB |
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NC |
4 |
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OLP |
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Iover |
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Reset |
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Rsense |
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Vth |
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S |
Q |
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VSD |
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OVP |
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Min.20V |
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TSD |
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A/R |
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1 |
GND |
Figure 2. Functional Block Diagram of FSDM311
2
FSDM311
Pin Definitions
Pin Number |
Pin Name |
Pin Function Description |
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1 |
GND |
Sense FET source terminal on primary side and internal control ground. |
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Positive supply voltage input. Although connected to an auxiliary |
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transformer winding, current is supplied from pin 8 (Vstr) via an internal |
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2 |
Vcc |
switch during startup (see Internal Block Diagram section). It is not until Vcc |
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reaches the UVLO upper threshold (8.7V) that the internal start-up switch |
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opens and device power is supplied via the auxiliary transformer winding. |
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The feedback voltage pin is the inverting input to the PWM comparator with |
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nominal input levels between 0.5Vand 2.5V. It has a 0.40mA current source |
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connected internally while a capacitor and opto coupler are typically |
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connected externally. A feedback voltage of 4.5Vtriggers overload |
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3 |
Vfb |
protection |
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(OLP). There is a time delay while charging between 3V and 4.5V using an |
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internal 5uA current source, which prevents false triggering under transient |
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conditions but still allows the protection mechanism to operate under true |
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overload conditions. |
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The startup pin connects directly to the rectified AC line voltage source for |
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5 |
Vstr |
FSDM311. For the FSDM311, at start up the internal switch supplies internal |
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bias and charges an external storage capacitor placed between the Vcc pin |
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and ground. Once this reaches 9V, the internal current source is disabled. |
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The Drain pin is designed to connect directly to the primary lead of the |
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6, 7, 8 |
Drain |
transformer and is capable of switching a maximum of 650V. Minimizing the |
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length of the trace connecting this pin to the transformer will decrease |
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leakage inductance. |
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Pin Configuration
8DIP
8LSOP
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Drain |
GND |
1 |
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8 |
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Vcc |
2 |
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7 |
Drain |
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Vfb |
3 |
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6 |
Drain |
Ipk |
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Vstr |
4 |
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5 |
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Figure 3. Pin Configuration (Top View)
3
FSDM311
Absolute Maximum Ratings
(Ta=25° C unless otherwise specified)
Parameter |
Symbol |
Value |
Unit |
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Maximum Vstr Pin Voltage |
VSTR,MAX |
650 |
V |
Maximum Drain Pin Voltage |
VDRAIN,MAX |
650 |
V |
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Drain-Gate Voltage (RGS=1MΩ ) |
VDGR |
650 |
V |
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Gate-Source (GND) Voltage |
VGS |
± 20 |
V |
Drain Current Pulsed (1) |
IDM |
1.5 |
ADC |
Continuous Drain Current (Tc=25° C) |
ID |
0.5 |
ADC |
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Continuous Drain Current (Tc=100° C) |
ID |
0.32 |
ADC |
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Single Pulsed Avalanche Energy (2) |
EAS |
10 |
mJ |
Maximum Supply Voltage |
VCC,MAX |
20 |
V |
Input Voltage Range |
VFB |
− 0.3 to Vstop |
V |
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Total Power Dissipation |
PD |
1.25 |
W |
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Operating Junction Temperature. |
TJ |
+150 |
° C |
Operating Ambient Temperature. |
TA |
-25 to +85 |
° C |
Storage Temperature Range. |
TSTG |
-55 to +150 |
° C |
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1.Repetitive rating: Pulse width limited by maximum junction temperature
2.L=24mH, starting Tj=25° C
Thermal Impedance
Parameter |
Symbol |
Value |
Unit |
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8DIP |
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Junction-to-Ambient Thermal |
θ JA(1) |
?(3) |
° C/W |
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θ JA(1) |
?(4) |
° C/W |
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Junction-to-Case Thermal |
θ JC(2) |
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° C/W |
Note:
1.Free standing without heatsink.
2.Measured on the GND pin close to plastic interface.
3.Soldered to 100mm2 copper clad.
4.Soldered to 300mm2 copper clad.
4
FSDM311
Electrical Characteristics (Sense FET Part)
(Ta = 25° C unless otherwise specified)
Parameter |
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Symbol |
Condition |
Min. |
Typ. |
Max. |
Unit |
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Sense FET SECTION |
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Drain-Source Breakdown Voltage |
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BVDSS |
VGS=0V, ID=50µ A |
650 |
720 |
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V |
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VDS=Max. Rating, |
- |
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25 |
µ |
A |
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VGS=0V |
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Zero Gate Voltage Drain Current |
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IDSS |
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VDS=0.8Max. Rating, |
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200 |
µ |
A |
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VGS=0V, TC=125° C |
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Static Drain-Source on Resistance |
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RDS(ON) |
VGS=10V, ID=0.5A |
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14 |
19 |
Ω |
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(Note) |
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Forward Trans conductance (Note) |
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gfs |
VDS=50V, ID=0.5A |
1.0 |
1.3 |
- |
S |
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Input Capacitance |
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CISS |
VGS=0V, VDS=25V, |
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162 |
- |
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Output Capacitance |
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COSS |
- |
18 |
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pF |
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f=1MHz |
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Reverse Transfer Capacitance |
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CRSS |
- |
3.8 |
- |
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Turn on Delay Time |
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td(on) |
VDD=0.5B VDSS, |
- |
9.5 |
- |
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ID=1.0A |
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Rise Time |
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tr |
- |
19 |
- |
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(MOSFET switching time |
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ns |
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Turn Off Delay Time |
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td(off) |
- |
33 |
- |
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is essentially |
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Fall Time |
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tf |
independent of |
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42 |
- |
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operating temperature) |
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Total Gate Charge |
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Qg |
VGS=10V, ID=1.0A, |
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7.0 |
- |
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(Gate-Source + Gate-Drain) |
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VDS=0.5B VDSS |
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(MOSFET switching time |
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Gate-Source Charge |
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Qgs |
- |
3.1 |
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nC |
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is essentially |
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Gate-Drain (Miller) Charge |
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Qgd |
independent of operating |
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0.4 |
- |
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temperature) |
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Note: |
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1. Pulse test: Pulse width ≤ 300 S, duty ≤ |
2% |
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2. |
S = |
1 |
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--- |
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R |
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5