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M27C4001

4 Megabit (512K x 8) UV EPROM and OTP ROM

VERY FAST ACCESS TIME: 70ns

COMPATIBLE with HIGH SPEED MICROPROCESSORS, ZERO WAIT STATE

LOW POWER ºCMOSº CONSUMPTION:

±Active Current 30mA at 5MHz

±Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V

ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING

PROGRAMMING TIMES of AROUND 48sec. (PRESTO II ALGORITHM)

DESCRIPTION

The M27C4001 is a high speed 4 Megabit UV erasable and programmable memory (EPROM) ideally suited for microprocessor systems requiring large programs. It isorganised as 524,288 by 8 bits.

The 32 pin Window Ceramic Frit-Seal Dual-in-Line and Leadless Chip Carrier packages have transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27C4001 is offered in both Plastic Leaded Chip Carrier and Plastic Thin Small Outline packages.

Table 1. Signal Names

A0 - A18

Address Inputs

Q0 - Q7

Data Outputs

E

Chip Enable

G

Output Enable

VPP

Program Supply

VCC

Supply Voltage

VSS

Ground

28

1

FDIP32W (F)

LCCC32W (L)

PLCC32 (C)

TSOP32 (N)

 

8 x 20mm

Figure 1. Logic Diagram

VCC

VPP

19

8

A0-A18

Q0-Q7

E M27C4001

G

VSS

AI00721B

March 1995

1/14

M27C4001

Figure 2A. DIP Pin Connections

VPP

1

32

VCC

A16

2

31

A18

A15

3

30

A17

A12

4

29

A14

A7

5

28

A13

A6

6

27

A8

A5

7

26

A9

A4

8

M27C4001 25

A11

A3

9

24

G

A2

10

23

A10

A1

11

22

E

A0

12

21

Q7

Q0

13

20

Q6

Q1

14

19

Q5

Q2

15

18

Q4

VSS

16

17

Q3

 

 

AI00722

 

Figure 2B. LCC Pin Connections

 

A12

A15

A16

PP

CC

A18

A17

 

 

V

V

 

A7

 

 

 

1

32

 

 

A14

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

A13

A5

 

 

 

 

 

 

 

A8

A4

 

 

 

 

 

 

 

A9

A3

9

 

M27C4001

 

25

A11

A2

 

 

 

 

 

 

 

G

A1

 

 

 

 

 

 

 

A10

A0

 

 

 

 

 

 

 

E

Q0

 

 

 

17

 

 

 

Q7

 

 

 

 

 

 

 

 

 

Q1

Q2

SS Q3

Q4

Q5

Q6

 

 

 

 

V

 

 

 

 

 

AI00723

Figure 2C. TSOP Pin Connections

A11

1

 

32

G

A9

 

 

 

A10

A8

 

 

 

E

A13

 

 

 

Q7

A14

 

 

 

Q6

A17

 

 

 

Q5

A18

 

 

 

Q4

VCC

8

M27C4001

25

Q3

VPP

9

(Normal)

24

VSS

A16

 

 

 

Q2

A15

 

 

 

Q1

A12

 

 

 

Q0

A7

 

 

 

A0

A6

 

 

 

A1

A5

 

 

 

A2

A4

16

 

17

A3

 

 

AI01155B

 

DEVICE OPERATION

The modes of operations of the M27C4001 are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on A9 for Electronic Signature.

Read Mode

The M27C4001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV.

Standby Mode

The M27C4001 has a standby mode which reduces the active current from 30mA to 100μA. The M27C4001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standbymode, the outputs are in a high impedance state, independent of the G input.

2/14

 

 

 

M27C4001

Table 2. Absolute Maximum Ratings (1)

 

 

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

±40 to 125

°C

TBIAS

Temperature Under Bias

±50 to 125

°C

TSTG

Storage Temperature

±65 to 150

°C

(2)

Input or Output Voltages (except A9)

±2 to 7

V

VIO

VCC

Supply Voltage

±2 to 7

V

(2)

A9 Voltage

±2 to 13.5

V

VA9

VPP

Program Supply Voltage

±2 to 14

V

Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

Table 3. Operating Modes

Mode

E

G

A9

VPP

Q0 - Q7

Read

VIL

VIL

X

VCC or VSS

Data Out

Output Disable

VIL

VIH

X

VCC or VSS

Hi-Z

Program

VIL Pulse

VIH

X

VPP

Data In

Verify

VIH

VIL

X

VPP

Data Out

Program Inhibit

VIH

VIH

X

VPP

Hi-Z

Standby

VIH

X

X

VCC or VSS

Hi-Z

Electronic Signature

VIL

VIL

VID

VCC

Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V

 

 

 

 

 

Table 4. Electronic Signature

Identifier

A0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Hex Data

Manufacturer's Code

VIL

0

0

1

0

0

0

0

0

20h

Device Code

VIH

0

1

0

0

0

0

0

1

41h

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a.the lowest possible memory power dissipation,

b.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

3/14

M27C4001

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times

20ns

Input Pulse Voltages

0.4V to 2.4V

Input and Output Timing Ref. Voltages

0.8V to 2.0V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 3. AC Testing Input Output Waveforms

2.4V

2.0V

0.8V

0.4V

AI00826

Figure 4. AC Testing Load Circuit

1.3V

1N914

3.3kΩ

DEVICE

UNDER OUT TEST

CL = 100pF

CL includes JIG capacitance

AI00828

Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

CIN

Input Capacitance

VIN = 0V

 

6

pF

COUT

Output Capacitance

VOUT = 0V

 

12

pF

Note: 1. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A18

VALID

 

tAVQV

tAXQX

E

 

tGLQV

tEHQZ

 

G

 

tELQV

tGHQZ

 

Q0-Q7

Hi-Z

DATA OUT

 

AI00724

4/14

 

 

 

 

 

 

 

 

 

 

 

M27C4001

Table 6. Read Mode DC Characteristics (1)

 

 

 

 

 

 

 

 

 

 

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

 

 

 

 

 

Symbol

 

Parameter

 

Test Condition

 

Min

 

Max

 

Unit

ILI

Input Leakage Current

 

 

0V VIN VCC

 

 

 

 

±10

 

μA

ILO

Output Leakage Current

 

0V VOUT VCC

 

 

 

 

±10

 

μA

ICC

Supply Current

 

E = VIL, G = VIL,

 

 

 

 

30

 

mA

IOUT = 0mA, f = 5MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICC1

Supply Current (Standby) TTL

 

 

E = VIH

 

 

 

 

1

 

mA

ICC2

Supply Current (Standby) CMOS

 

 

E > VCC ± 0.2V

 

 

 

 

100

 

μA

IPP

Program Current

 

 

VPP = VCC

 

 

 

 

10

 

μA

VIL

Input Low Voltage

 

 

 

 

±0.3

 

0.8

 

V

(2)

Input High Voltage

 

 

 

 

2

 

VCC + 1

V

VIH

 

 

 

 

 

VOL

Output Low Voltage

 

 

IOL = 2.1mA

 

 

 

 

0.4

 

V

VOH

Output High Voltage TTL

 

 

IOH = ±400μA

 

2.4

 

 

 

V

Output High Voltage CMOS

 

 

IOH = ±100μA

 

VCC ± 0.7V

 

 

 

V

 

 

 

 

 

 

 

Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

 

 

 

 

2. Maximum DC voltage on Output is VCC +0.5V.

 

 

 

 

 

 

 

 

 

 

Table 7A. Read Mode AC Characteristics (1)

 

 

 

 

 

 

 

 

 

 

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

 

 

 

 

 

 

 

 

 

 

 

 

M27C4001

 

 

 

Symbol

Alt

Parameter

 

 

Test Condition

-70

-80

-90

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

 

tAVQV

tACC

Address Valid to Output Valid

 

 

E = VIL, G = VIL

 

70

 

80

 

90

ns

tELQV

tCE

Chip Enable Low to Output Valid

 

G = VIL

 

70

 

80

 

90

ns

tGLQV

tOE Output Enable Low to Output Valid

E = VIL

 

35

 

40

 

40

ns

(2)

tDF

Chip Enable High to Output Hi-Z

 

G = VIL

0

30

0

30

0

30

ns

tEHQZ

 

(2)

tDF

Output Enable High to Output Hi-Z

E = VIL

0

30

0

30

0

30

ns

tGHQZ

tAXQX

tOH

Address Transition to

 

 

E = VIL, G = VIL

0

 

0

 

0

 

ns

Output Transition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7B. Read Mode AC Characteristics (1)

 

 

 

 

 

 

 

 

 

 

(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

 

 

 

 

 

 

 

 

 

 

 

 

M27C4001

 

 

 

Symbol

Alt

Parameter

 

 

Test Condition

-10

-12

-15

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

 

tAVQV

tACC

Address Valid to Output Valid

 

 

E = VIL, G = VIL

 

100

 

120

 

150

ns

tELQV

tCE

Chip Enable Low to Output Valid

 

G = VIL

 

100

 

120

 

150

ns

tGLQV

tOE

Output Enable Low to Output Valid

E = VIL

 

50

 

60

 

60

ns

(2)

tDF

Chip Enable High to Output Hi-Z

 

G = VIL

0

30

0

40

0

50

ns

tEHQZ

 

(2)

tDF

Output Enable High to Output Hi-Z

E = VIL

0

30

0

40

0

50

ns

tGHQZ

tAXQX

tOH

Address Transition to

 

 

E = VIL, G = VIL

0

 

0

 

0

 

ns

Output Transition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.

5/14

Источник: https://studfile.net/preview/16502915/