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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Designer's Data Sheet

Medium Power Surface Mount Products

Complementary TMOS Field Effect Transistors

MiniMOS devices are an advanced series of power MOSFETs which utilize Motorola's High Cell Density HDTMOS process.

These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding

high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.

•Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life

•Logic Level Gate Drive Ð Can Be Driven by Logic ICs

•Miniature SO-8 Surface Mount Package Ð Saves Board Space

•Diode Is Characterized for Use In Bridge Circuits

•Diode Exhibits High Speed, With Soft Recovery

•IDSS Specified at Elevated Temperature

•Avalanche Energy Specified

•Mounting Information for SO-8 Package Provided

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)

D

N±Channel

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

VGS, GATE±TO±SOURCE VOLTAGE (VOLTS)

Figure 3. On±Resistance versus

Gate±To±Source Voltage

P±Channel

0.6

ID = 1 A

0.5

TJ = 25°C

0.4

0.3

0.2

0.1

0

Figure 3. On±Resistance versus

Gate±To±Source Voltage

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain±gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input

current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following:

tr = Q2 x RG/(VGG ± VGSP) tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn±on and turn±off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG ± VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off±state condition when cal-

culating td(on) and is read at a voltage corresponding to the on±state when calculating td(off).

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.