Материал: 74HC244A
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
High±Performance Silicon±Gate CMOS
The MC54/74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be used with 3±state memory address drivers, clock drivers, and other bus±oriented systems. The device has noninverting outputs and two active±low output enables.
The HC244A is similar in function to the HC240A and HC241A.
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2 to 6 V
•Low Input Current: 1 μA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 136 FETs or 34 Equivalent Gates
LOGIC DIAGRAM
A1 |
2 |
18 |
YA1 |
A2 |
4 |
16 |
YA2 |
A3 |
6 |
14 |
YA3 |
A4 |
8 |
12 |
YA4 |
DATA |
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NONINVERTING |
INPUTS |
11 |
9 |
OUTPUTS |
B1 |
YB1 |
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B2 |
13 |
7 |
YB2 |
B3 |
15 |
5 |
YB3 |
B4 |
17 |
3 |
YB4 |
PIN 20 = VCC OUTPUT 
ENABLE A 1 PIN 10 = GND
ENABLES
ENABLE B 19
MC54/74HC244A
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J SUFFIX |
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20 |
CERAMIC PACKAGE |
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CASE 732±03 |
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1 |
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N SUFFIX |
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20 |
PLASTIC PACKAGE |
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CASE 738±03 |
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1 |
20 |
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DW SUFFIX |
1 |
SOIC PACKAGE |
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CASE 751D±04 |
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20 |
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SD SUFFIX |
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SSOP PACKAGE |
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1 |
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CASE 940C±03 |
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20 |
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DT SUFFIX |
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TSSOP PACKAGE |
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1 |
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CASE 948E±02 |
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ORDERING INFORMATION |
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MC54HCXXXAJ |
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Ceramic |
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MC74HCXXXAN |
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Plastic |
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MC74HCXXXADW |
SOIC |
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MC74HCXXXASD |
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SSOP |
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MC74HCXXXADT |
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TSSOP |
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PIN ASSIGNMENT
ENABLE A |
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1 |
20 |
VCC |
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A1 |
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2 |
19 |
ENABLE B |
YB4 |
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3 |
18 |
YA1 |
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A2 |
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4 |
17 |
B4 |
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YB3 |
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5 |
16 |
YA2 |
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A3 |
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6 |
15 |
B3 |
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YB2 |
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7 |
14 |
YA3 |
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A4 |
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8 |
13 |
B2 |
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YB1 |
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9 |
12 |
YA4 |
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GND |
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10 |
11 |
B1 |
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FUNCTION TABLE
Inputs |
Outputs |
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Enable A, |
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Enable B |
A, B |
YA, YB |
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L |
L |
L |
L |
H |
H |
H |
X |
Z |
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Z = high impedance
10/95
Motorola, Inc. 1995 |
REV 6 |
MC54/74HC244A
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
± 1.5 to VCC + 1.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
Iin |
DC Input Current, per Pin |
± 20 |
mA |
Iout |
DC Output Current, per Pin |
± 35 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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SSOP or TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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(Plastic DIP, SOIC, SSOP or TSSOP Package) |
260 |
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(Ceramic DIP) |
300 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
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2.0 |
6.0 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
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TA |
Operating Temperature, All Package Types |
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± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
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(Figure 1) |
VCC = 4.5 V |
0 |
500 |
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VCC = 6.0 V |
0 |
400 |
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
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± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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VIH |
Minimum High±Level Input |
Vout = VCC ± 0.1 V |
2.0 |
1.5 |
1.5 |
1.5 |
V |
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Voltage |
|Iout| v 20 |
μA |
4.5 |
3.15 |
3.15 |
3.15 |
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6.0 |
4.2 |
4.2 |
4.2 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V |
2.0 |
0.5 |
0.5 |
0.5 |
V |
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Voltage |
|Iout| v 20 μA |
4.5 |
1.35 |
1.35 |
1.35 |
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6.0 |
1.8 |
1.8 |
1.8 |
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VOH |
Minimum High±Level Output |
Vin = VIH |
μA |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
4.4 |
4.4 |
4.4 |
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6.0 |
5.9 |
5.9 |
5.9 |
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Vin = VIH |
|Iout| v 6.0 mA |
4.5 |
3.98 |
3.84 |
3.70 |
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|Iout| v 7.8 mA |
6.0 |
5.48 |
5.34 |
5.20 |
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VOL |
Maximum Low±Level Output |
Vin = VIL |
μA |
2.0 |
0.1 |
0.1 |
0.1 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
0.1 |
0.1 |
0.1 |
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6.0 |
0.1 |
0.1 |
0.1 |
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Vin = VIL |
|Iout| v 6.0 mA |
4.5 |
0.26 |
0.33 |
0.40 |
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|Iout| v 7.8 mA |
6.0 |
0.26 |
0.33 |
0.40 |
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Iin |
Maximum Input Leakage Current |
Vin = VCC or GND |
6.0 |
± 0.1 |
± 1.0 |
± 1.0 |
μA |
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MOTOROLA |
2 |
MC54/74HC244A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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IOZ |
Maximum Three±State |
Output in High±Impedance State |
6.0 |
± 0.5 |
± 5.0 |
± 10 |
μA |
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Leakage Current |
Vin = VIL or VIH |
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Vout = VCC or GND |
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ICC |
Maximum Quiescent Supply |
Vin = VCC or GND |
6.0 |
4 |
40 |
160 |
μA |
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Current (per Package) |
Iout = 0 μA |
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NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
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Guaranteed Limit |
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VCC |
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± 55 to |
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Symbol |
Parameter |
V |
25_C |
v85_C |
v125_C |
Unit |
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tPLH, |
Maximum Propagation Delay, A to YA or B to YB |
2.0 |
96 |
115 |
135 |
ns |
tPHL |
(Figures 1 and 3) |
4.5 |
18 |
23 |
27 |
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6.0 |
15 |
20 |
23 |
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tPLZ, |
Maximum Propagation Delay, Output Enable to YA or YB |
2.0 |
110 |
140 |
165 |
ns |
tPHZ |
(Figures 2 and 4) |
4.5 |
22 |
28 |
33 |
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6.0 |
19 |
24 |
28 |
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tPZL, |
Maximum Propagation Delay, Output Enable to YA or YB |
2.0 |
110 |
140 |
165 |
ns |
tPZH |
(Figures 2 and 4) |
4.5 |
22 |
28 |
33 |
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6.0 |
19 |
24 |
28 |
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tTLH, |
Maximum Output Transition Time, Any Output |
2.0 |
60 |
75 |
90 |
ns |
tTHL |
(Figures 1 and 3) |
4.5 |
12 |
15 |
18 |
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6.0 |
10 |
13 |
15 |
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Cin |
Maximum Input Capacitance |
Ð |
10 |
10 |
10 |
pF |
Cout |
Maximum Three±State Output Capacitance (Output in |
Ð |
15 |
15 |
15 |
pF |
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High±Impedance State) |
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NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).
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Typical @ 25°C, VCC = 5.0 V |
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CPD |
Power Dissipation Capacitance (Per Buffer)* |
34 |
pF |
*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
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SWITCHING WAVEFORMS |
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tr |
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tf |
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VCC |
DATA INPUT |
90% |
VCC |
ENABLE |
50% |
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A OR B |
50% |
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A OR B |
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GND |
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10% |
GND |
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tPZL |
tPLZ |
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tPLH |
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HIGH |
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tPHL |
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OUTPUT |
90% |
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OUTPUT Y |
50% |
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IMPEDANCE |
YA OR YB |
50% |
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10% |
VOL |
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10% |
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tPZH |
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tPHZ |
VOH |
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t |
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t |
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90% |
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TLH |
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THL |
OUTPUT Y |
50% |
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HIGH |
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IMPEDANCE |
Figure 1. |
Figure 2. |
3 |
MOTOROLA |
MC54/74HC244A
TEST CIRCUITS
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TEST POINT |
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TEST POINT |
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OUTPUT |
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OUTPUT |
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1 kΩ |
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CONNECT TO VCC WHEN |
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DEVICE |
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DEVICE |
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TESTING tPLZ AND tPZL. |
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CONNECT TO GND WHEN |
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UNDER |
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CL* |
UNDER |
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CL* |
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TESTING tPHZ AND tPZH. |
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TEST |
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TEST |
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* Includes all probe and jig capacitance |
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* Includes all probe and jig capacitance |
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Figure 3. Test Circuit |
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Figure 4. Test Circuit |
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PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
Output enables (active±low). When a low level is applied
to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the output± enable pins, these outputs are either noninverting outputs or high±impedance outputs.
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
INVERTERS
DATA 
VCC INPUT 
A OR B
YA
OR
YB
ENABLE A OR
ENABLE B
MOTOROLA |
4 |
MC54/74HC244A
OUTLINE DIMENSIONS
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J SUFFIX |
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CERAMIC PACKAGE |
20 |
11 |
CASE 732±03 |
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ISSUE E |
1 |
10 |
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B |
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A |
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F |
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C |
L |
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N |
J |
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H |
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K |
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G |
M |
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D |
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SEATING |
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PLANE |
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NOTES:
1.LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION.
2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3.DIMENSIONS A AND B INCLUDE MENISCUS.
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MILLIMETERS |
INCHES |
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DIM |
MIN |
MAX |
MIN |
MAX |
A |
23.88 |
25.15 |
0.940 |
0.990 |
B |
6.60 |
7.49 |
0.260 |
0.295 |
C |
3.81 |
5.08 |
0.150 |
0.200 |
D |
0.38 |
0.56 |
0.015 |
0.022 |
F |
1.40 |
1.65 |
0.055 |
0.065 |
G |
2.54 BSC |
0.100 BSC |
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H |
0.51 |
1.27 |
0.020 |
0.050 |
J |
0.20 |
0.30 |
0.008 |
0.012 |
K |
3.18 |
4.06 |
0.125 |
0.160 |
L |
7.62 BSC |
0.300 BSC |
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M |
0 |
15 |
0 |
15 |
N |
0.25 |
1.02 |
0.010 |
0.040 |
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N SUFFIX |
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±A± |
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PLASTIC PACKAGE |
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CASE 738±03 |
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NOTES: |
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ISSUE E |
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1. DIMENSIONING AND TOLERANCING PER ANSI |
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20 |
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11 |
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Y14.5M, 1982. |
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B |
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2. CONTROLLING DIMENSION: INCH. |
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3. DIMENSION L TO CENTER OF LEAD WHEN |
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1 |
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10 |
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FORMED PARALLEL. |
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4. DIMENSION B DOES NOT INCLUDE MOLD |
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C |
L |
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FLASH. |
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INCHES |
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MILLIMETERS |
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DIM |
MIN |
MAX |
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MIN |
MAX |
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A |
1.010 |
1.070 |
25.66 |
27.17 |
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±T± |
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B |
0.240 |
0.260 |
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6.10 |
6.60 |
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K |
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C |
0.150 |
0.180 |
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3.81 |
4.57 |
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SEATING |
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D |
0.015 |
0.022 |
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0.39 |
0.55 |
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M |
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E |
0.050 BSC |
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1.27 BSC |
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PLANE |
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E |
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N |
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F |
0.050 |
0.070 |
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1.27 |
1.77 |
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G |
0.100 BSC |
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2.54 BSC |
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G |
F |
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J |
0.008 |
0.015 |
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0.21 |
0.38 |
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J 20 PL |
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K |
0.110 |
0.140 |
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2.80 |
3.55 |
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D 20 PL |
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0.25 (0.010) M |
T |
B |
M |
L |
0.300 BSC |
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7.62 BSC |
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M |
0 |
15 |
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0 |
15 |
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0.25 (0.010) M |
T |
A M |
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N |
0.020 |
0.040 |
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0.51 |
1.01 |
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DW SUFFIX |
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±A± |
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PLASTIC SOIC PACKAGE |
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NOTES: |
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CASE 751D±04 |
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1. DIMENSIONING AND TOLERANCING PER |
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ANSI Y14.5M, 1982. |
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20 |
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11 |
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ISSUE E |
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2. CONTROLLING DIMENSION: MILLIMETER. |
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3. DIMENSIONS A AND B DO NOT INCLUDE |
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MOLD PROTRUSION. |
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±B± |
10X P |
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4. MAXIMUM MOLD PROTRUSION 0.150 |
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(0.006) PER SIDE. |
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0.010 (0.25) M |
B M |
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5. DIMENSION D DOES NOT INCLUDE |
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DAMBAR PROTRUSION. ALLOWABLE |
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1 |
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10 |
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DAMBAR PROTRUSION SHALL BE 0.13 |
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(0.005) TOTAL IN EXCESS OF D DIMENSION |
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AT MAXIMUM MATERIAL CONDITION. |
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20X D |
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J |
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MILLIMETERS |
INCHES |
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0.010 (0.25) M |
T |
A |
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B |
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DIM |
MIN |
MAX |
MIN |
MAX |
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S |
S |
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A |
12.65 |
12.95 |
0.499 |
0.510 |
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B |
7.40 |
7.60 |
0.292 |
0.299 |
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F |
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C |
2.35 |
2.65 |
0.093 |
0.104 |
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D |
0.35 |
0.49 |
0.014 |
0.019 |
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F |
0.50 |
0.90 |
0.020 |
0.035 |
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R X 45 |
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G |
1.27 BSC |
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0.050 BSC |
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J |
0.25 |
0.32 |
0.010 |
0.012 |
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K |
0.10 |
0.25 |
0.004 |
0.009 |
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M |
0 |
7 |
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0 |
7 |
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C |
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P |
10.05 |
10.55 |
0.395 |
0.415 |
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R |
0.25 |
0.75 |
0.010 |
0.029 |
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±T± |
SEATING |
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PLANE |
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M |
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18X G |
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K |
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5 |
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MOTOROLA |